(1) Field of the Invention
The present invention relates to a wiring board for mounting a semiconductor element.
(2) Description of the Related Art
Conventionally, as a wiring board for mounting a semiconductor element, a wiring board having a multilayer structure formed by a buildup technique is used (Japanese Unexamined Patent Application Publication No. 2010-259390). A conventional example of this wiring board is shown in FIGS. 10 and 11. As shown in FIG. 10, a conventional wiring board 200 is formed such that a buildup portion 32 is laminated on each of upper and lower surfaces of a core board 31.
The core board 31 includes a core insulating plate 34 having a plurality of through holes 33, and a core wiring conductor 35 adhered to an inside of the through hole 33 and upper and lower surfaces of the core insulating plate 34. The core insulating plate 34 is formed of a fiber-reinforced resin plate provided by impregnating glass cloth with a thermosetting resin such as epoxy resin.
The buildup portion 32 is formed by alternately laminating a buildup insulating layer 37 having a plurality of via holes 36, and a buildup wiring conductor 38 adhered to an inside of the via hole 36 and a surface of the buildup insulating layer 37, on each of the upper and lower surfaces of the core board 31. The buildup insulating layer 37 is formed of a filler containing resin layer in which an inorganic insulating filler composed of silicon oxide is dispersed in a thermosetting resin such as epoxy resin.
A solder resist layer 39 is adhered to a surface of the buildup portion 32 laminated on each of the upper and lower surfaces of the core board 31, in order to protect the buildup wiring conductor 38 provided in each of the uppermost and lowermost layers. The solder resist layer 39 is made of thermosetting resin such as acrylic-modified epoxy resin.
A mounting portion 32A for mounting a semiconductor element 53 is provided in a center of an upper surface of the buildup portion 32 on an upper surface side. The mounting portion 32A is a rectangular region having a size corresponding to the semiconductor element 53. In general, each side of the mounting portion 32A is parallel to an outer peripheral side of the wiring board 200. A plurality of semiconductor element connection pads 40 each formed of the buildup wiring conductor 38 adhered onto an uppermost buildup insulating layer 37 on the upper surface side are formed in the mounting portion 32A. Several hundreds to several thousands of the semiconductor element connection pads 40 are arranged in a shape of a lattice.
A plurality of external connection pads 41 each formed of the buildup wiring conductor 38 adhered to a lower surface of a lowermost buildup insulating layer 37 on a lower layer side are formed on a lower surface of the buildup portion 32 on a lower surface side. Several hundreds to several thousands of the external connection pads 41 are arranged in a shape of a lattice. The semiconductor element connection pad 40 and the external connection pad 41 corresponding to each other are electrically connected through the buildup wiring conductor 38 and the core wiring conductor 35.
By the way, as for the current semiconductor element, high-speed and high-capacity transmission are remarkably increased. In tandem with it, a wiring board for mounting the semiconductor element is required to be configured such that an electric loss is low at the time of high-frequency transmission. Therefore, as for the wiring board having a transmission path to transmit a high frequency signal, the wiring board has differential lines as the transmission paths for the high frequency signal in many cases. The differential lines are provided such that two transmission lines are adjacently provided side by side with a predetermined distance provided between them. When the signals having opposite phases are transmitted in the transmission lines, the transmission loss can be reduced at the time of the high frequency transmission.
The differential lines will be described with reference to FIGS. 11 and 12. FIG. 11 is a top view of the wiring board 200 shown in FIG. 10, and mainly shows a couple of differential lines. Referring to FIG. 11, an outline of the wiring board 200 and the semiconductor element connection pads 40 are shown by solid lines, and a pair of wiring conductors 42P and 42P and a pair of external connection pads 41P and 41P for configuring the differential lines in an inside part and a lower surface of the wiring board 200 are shown by dotted lines. The semiconductor element mounting portion 32A is shown by two-dot chain line. FIG. 12 is a perspective view only showing the differential lines extracted from FIG. 11.
As shown in FIGS. 11 and 12, the semiconductor element connection pads 40 have a pair of connection pads 40P and 40P for the differential lines. The pair of semiconductor element connection pads 40P and 40P is adjacently arranged. The external connection pads 41 have the pair of external connection pads 41P and 41P corresponding to the pair of semiconductor element connection pads 40P and 40P, respectively. The pair of semiconductor element connection pads 40P and 40P is electrically connected to the pair of external connection pads 41P and 41P, through the pair of strip-shaped wiring conductors 42P and 42P provided in the buildup wiring conductor 38 on the upper surface side.
The pair of strip-shaped wiring conductors 42P and 42P extend from circular first lands 42B positioned below the corresponding pair of semiconductor element connection pads 40P and 40P, to circular second lands 42C positioned above the pair of external connection pads 41P and 41P. The pair of semiconductor element connection pads 40P and 40P is electrically connected to the first lands 42B in the pair of strip-shaped wiring conductors 42P and 42P through via holes 36 positioned just under the pair of semiconductor element connection pads 40P and 40P. The pair of external connection pads 41P and 41P is electrically connected to the second lands 42C in the pair of strip-shaped wiring conductors 42P and 42P through the through holes 33 and the plurality of via holes 36 provided above the pair of external connection pads 41P and 41P. The pair of strip-shaped wiring conductors 42P and 42P has parallel extending portions 42A which extend in parallel to each other, except for the vicinity of connection ends to the pair of semiconductor element connection pads 40P and 40P (the first lands 42B and connection portions 42D), and the vicinity of connection ends to the pair of external connection pads 41P and 41P (the second lands 42C and connection portions 42E). As for the parallel extending portion 42A, a width of the strip-shaped wiring conductor and a distance between the adjacent strip-shaped wiring conductors are adjusted so that a characteristic impedance of the pair of strip-shaped wiring conductors 42P and 42P shows 100Ω, for example.
FIG. 13 is a partial perspective view showing only an extracted part of the core wiring conductor 35 and the plurality of buildup wiring conductors 38 on the upper surface side.
A ground or power supply conductor G1 is arranged in the uppermost buildup wiring conductor 38 positioned on the upper surface side of the pair of strip-shaped wiring conductors 42P and 42P, so as to be opposed to a region of the same layer as the pair of strip-shaped wiring conductors 42P and 42P, except for the connection end to the pair of semiconductor element connection pads 40P and 40P, in the pair of strip-shaped wiring conductors 42P and 42P and its vicinity. Ground or power supply conductor G2 is arranged in the buildup wiring conductor 38 serving as the same layer as the pair of strip-shaped wiring conductors 42P and 42P, so as to surround the pair of strip-shaped wiring conductors 42P and 42P with a predetermined distance provided between them. Ground or power supply conductors G3 to G5 are arranged in the buildup wiring conductor 38 and the core wiring conductor 35 provided below the pair of strip-shaped wiring conductors 42P and 42P so as to be opposed to the region of the same layer as the pair of strip-shaped wiring conductors 42P and 42P, except for the connection end to the pair of external connection pads 41P and 41P, in the pair of strip-shaped wiring conductors 42P and 42P and its vicinity. An oval opening 55 is formed in the ground or power supply conductors G3 to G5 so as to surround the via holes 36 and the through holes 33 which connect the pair of strip-shaped wiring conductors 42P and 42P to the pair of external connection pads 41P and 41P, with a predetermined distance provided between them. As for the differential lines, a line width of the strip-shaped wiring conductor and a distance between the adjacent strip-shaped wiring conductors in the pair of strip-shaped wiring conductors 42P and 42P, and a distance from the ground or power supply conductor G1 to G5 are adjusted so that a characteristic impedance of the pair of strip-shaped wiring conductors 42P and 42P shows about 100Ω, for example.
According to the wiring board 200, an electrode 54 of a semiconductor element 53 is connected to the semiconductor element connection pad 40 through a solder so that the semiconductor element 53 is mounted on the wiring board 200, and the pair of external connection pads 41 and 41 is connected to a wiring conductor of an external electric circuit board through a solder. As a result, the semiconductor element 53 mounted on the wiring board 200 is electrically connected to the external electric circuit board through the wiring board 200.
The conventional wiring board 200 is designed so that the characteristic impedance in the path from the pair of semiconductor element connection pads 40P and 40P to the pair of external connection pads 41P and 41P shows a value close to 100Ω, for example. However, in the case where the capacitive component is added to the electrodes 54 of the semiconductor element 53 connected to the pair of semiconductor element connection pads 40P and 40P, there is a problem that a reflection loss or transmission loss of the high frequency signal is increased between the electrodes 54 of the semiconductor element 53 and the pair of semiconductor element connection pads 40P and 40P.